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document number: MMA690XKQ rev. 5, 08/2012 freescale semiconductor data sheet: technical data ? 2010-2012 freescale semiconducto r, inc. all ri ghts reserved. high accuracy low g inertial sensor mems sensing, state machine asic the MMA690XKQ, a safeassure solution, is a dual axis, low g, xy, sensor based on freescale?s harmems technology, with an embedded dsp asic, allowing for additional processing of the digital signals. features ? sensitivity in x and y axes ? 3.5 or 5.0g full-scale range per axis ? aec-q100 qualified, rev. f, grade 2 (-40 t a 105 c) ? 50 hz second order low-pass filter ? unsigned 11-bits digital data output ? spi-compatible serial interface ? capture/hold input for system-wide syn chronization support ? 3.3 or 5.0v single supply operation ? on-chip temperature sensor and voltage regulator ? bi-directional internal self-test ? minimal external component requirements ? pb-free 16-pin qfn package ? pulse-code modulated output available for device evaluation typical applications ? with a 3.5g or 5.0g full scale r ange, the newly designed, high accuracy sensor, enables electronic stability control (esc) designers to accommodate higher original signal noise level without sacrificing resolution. ? tilt measurement ? electronic parking brake ordering information device name range shipping mma6900kq 3.5g tubes mma6901kq 5.0g mma6900kqr2 3.5g tape and reel mma6901kqr2 5.0g c ref v ss c rega c rega pcm_x v ssa cs /reset c reg cap /hold d in v pp c ref v cc sclk 1 2 3 4 5 6 7 8 12 11 10 9 16 15 14 13 pcm_y d out MMA690XKQ dual axis spi inertial sensor 16-pin qfn 98asa10571d case 1477-02 pin connections bottom view top view
sensors 2 freescale semiconductor, inc. MMA690XKQ section 1 introduction 1.1 introduction MMA690XKQ is a two-axis member of freesc ale?s family of spi-compatible accelerometers. these devices incorporate digital signal processing for filtering, trim, and data formatting. 1.2 serial communication configuration the serial communication configuration provides a 4-wire spi interf ace. device serial number, acceleration range, filter char- acteristics, and status information are available along with acceleration data via the spi. 1.3 block diagram a block diagram illustrating the major components of the design is shown in figure 1-1 . figure 1-1 block diagram spi v cc v ss d in d out sclk cs self-test c reg c ref v pp pcm_x interface temp. sensor ? converter voltage regulator g-cell (y) g-cell (x) control logic unit data array programmable ? converter clock internal monitor c rega cap /hold pcm pcm_y in 1 in 0 digital y out x out dsp temp (see figure 1-2 ) out control in status out pcm c ref c rega v ssa clock primary oscillator reference oscillator sinc filter sinc filter
sensors freescale semiconductor, inc. 3 MMA690XKQ figure 1-2 dsp block diagram 1.4 pin functions the pinout is illustrated in figure 1-3 . pin functions are described in the following paragraphs. when self-test is active, the output becomes more positive in both axes, if st1 is cleared or more negative in both axes if st1 is set, as described in section 2.1.3 . figure 1-3 pinout for MMA690XKQ offset, in 1 low-pass filter gain, linearity adjust output scaling dsp control digital out in 0 temp control in status out c ref v ss c rega c rega pcm_x v ssa cs /reset c reg cap /hold d in v pp top view 16-pin qfn package c ref v cc sclk 1 2 3 4 5 6 7 8 12 11 10 9 16 15 14 13 pcm_y d out response to static orientation within 1g field. to center of gravitational field x: -1g x: 0g y: 0g y: -1g x: +1g x: 0g y: 0g y: +1g
sensors 4 freescale semiconductor, inc. MMA690XKQ 1.4.1 v cc this pin supplies power to the device. careful printed wiring boar d layout and capacitor placement is critical to ensure best performance. an external bypass capacitor between this pin and v ss is required, as described in section 1.5 . 1.4.2 v ss this pin is the power supply return node for the digital circuitry on the MMA690XKQ device. 1.4.3 v ssa this pin is the power supply return node for analog circuitry on the MMA690XKQ device. an external bypass capacitor between this pin and v cc is required, as described in section 1.5 . 1.4.4 c reg this pin is connected to the internal digital circuitry power supply rail. an external filter capacitor must be connected betwe en this pin and v ss , as described in section 1.5 . 1.4.5 c rega these pins are connected in parallel to the internal analog circ uitry power supply rail. one or two external filter capacitors must be connected between these pins and v ssa , as described in section 1.5 . two pins are provided to support redundant connection to the printed wiring board assembly. redundant external capacitors may be connected to these pins for maximum reliability, as described in section 1.5 . 1.4.6 c ref these pins are connected in parallel to an internal reference vo ltage node utilized by the analog circuitry. one or two externa l filter capacitors must be connected between these pins and v ssa , as described shown in section 1.5 . two pins are provided to support redundant connection to the printed wiring board assembly . redundant external capacitors may be connected to these pins for maximum reliability, as described in section 1.5 . 1.4.7 v pp this pin should be tied directly to v ss . an internal pull-down device is connected to this pin to reduce the risk of unpredictable device operation in the even t that the connection to v ss opens. 1.4.8 sclk this input pin provides the serial clock to the spi port. the st ate of this pin is also used as a qualifier for externally-cont rolled reset. this input may be used to initiate device reset as described in section 1.4.9 and section 2.6 . an internal pull-down device is connected to this pin. 1.4.9 cs /reset this pin functions as the ch ip select input for the spi port. the state of the d in pin during low-to-high transitions of sclk is latched internally and d out is enabled when cs is at a logic low level. this pin may also be used to initiate a hardware reset. if cs is held low and sclk is held high for 512 s, the internal reset signal is asserted. this behavior is described in section 2.6 . an internal pull-up device is connected to this pin. 1.4.10 d out this pin functions as the serial data outpu t for the spi port. spi data transmitted on d out will have an odd number of logic ?1? bits set during normal 16-bit transfer, unless an internal oscill ator fault condition has been det ected. if an internal oscilla tor fault condition is present, d out is driven to a logic high level continuously when cs /reset is asserted. 1.4.11 d in this pin functions as the serial data input to the spi port. an internal pull-down device is connected to this pin. spi data re - ceived at d in must observe odd parity or a transient exception condition will be reported during the subsequent transfer. 1.4.12 cap /hold when this input pin is low, the spi acceleration result re gisters are updated by the dsp whenever a data sample becomes available. upon a low-to-high transition of cap /hold, the contents of the acceleration resu lt registers are frozen. the result reg- isters will not be updated so long as this pin remains at a logic ?1? level. this pin may be tied directly to v ss if the hold function is not desired.
sensors freescale semiconductor, inc. 5 MMA690XKQ an internal pulldown device is connected to this pin, however it is recommended that cap/hold either be driven by a logic output or tied to v ss in application circuits. if cap/hold is at logic level ?1 ? during initial startup and thro ugh the release of internal reset, the result register will be 0 counts, which is a reserved result, and should be discarded by the application. this state is exited by the next high-to-low transition of cap/hold. 1.4.13 pcm_x, pcm_y MMA690XKQ provides the option for a pulse code modulated (pcm) output function. the pcm output is activated when pcm_en is set in the devctl register. when the pcm function is enabled, the upper nine bits of the 11-bit scaled acceleration values are used to generate pcm signals proportional to incident respective acceleration, at 250 ns resolution. a simplified bl ock diagram of the pcm output is shown in figure 1-4 . figure 1-4 pcm output function block diagram output scaling oc[9:1] a 9-bit adder pcm_x/pcm_y b carry sum f clk = 4.0 mhz 9 9 9 d ff clk q d ff clk q d ff clk q d ff clk q d ff clk q d ff clk q d ff clk q d ff clk q d ff clk q
sensors 6 freescale semiconductor, inc. MMA690XKQ 1.5 external components the connections illustrated in figure 1-5 are recommended. careful printed wiring bo ard layout and component placement is essential for best performance. low esr capacitors must be connected to c reg and c rega pins for best performance. a ground- ed land area with solder mask should be placed under the package fo r improved shielding of the dev ice from external effects. if a land area is not provided, no signals should be routed beneath the package. figure 1-5 external components 1 f 100 nf 100 nf 1 f v cc MMA690XKQ v cc c rega c ref v ssa 100 nf c reg 1.0 f v cc MMA690XKQ c ref c rega 100 nf 1.0 f 100 nf 1.0 f recommended external component configuration alternate external component configuration v ss v cc c rega c ref v ssa c reg c ref c rega v ss
sensors freescale semiconductor, inc. 7 MMA690XKQ section 2 internal modules 2.1 data array a 400-bit data array allows each device to be customized. the a rray interface incorporates parity circuitry for fault detection along with a locking mechanism, to prevent unintended changes. port ions of the array are reserved for factory-programmed trim values. customer accessible data stored in the array are shown in the table 2-1 . addresses $00 - $0d are associated with the data array. a writabl e register at address $0e is provided for device control operations. two read-only registers at addr esses $0f and $10 provide status information. unused bits within the data array are always read as ?0? values. unprogrammed otp bits are also read as ?0? values. f: factory programmed otp location r: read-only register r/w: read/write register n/a: not applicable table 2-1. dsp configuration register location bit function type addr register 7 6 5 4 3 2 1 0 $00 sn0 sn[7] sn[6] sn[5] sn[4] sn[3] sn[2] sn[1] sn[0] f/r $01 sn1 sn[15] sn[14] sn[13] sn[12] sn[11] sn[10] sn[9] sn[8] $02 sn2 sn[23] sn[22] sn[21] sn[20] sn[19] sn[18] sn[17] sn[16] $03 sn3 sn[31] sn[30] sn[29] sn[28] sn[27] sn[26] sn[25] sn[24] $04 devcfg0 0 0 0 0 rng[3] rng[2] rng[1] rng[0] f/r $05 devcfg1 0 0 0 0 rng[3] rng[2] rng[1] rng[0] $06 devcfg2 0 0 0 0 0 0 0 0 $07 devcfg3 0 0 0 0 0 0 0 0 $08 devcfg4 0 0 0 0 0 0 0 0 $09 devcfg5 1 0 1 0 0 0 0 0 $0a axcfg_x 1 0 0 1 0 1 0 1 f/r $0b axcfg_y 1 0 0 1 0 1 0 1 $0c unused n/a $0d dspcfg 0 0 1 0 0 1 0 0 f/r $0e devctl res_1 res_0 ce pcm_en hpfb yinv st1 st0 r/w $0f temp temp[7] temp[6] temp[5] temp[4] temp[3] temp[2] temp[1] temp[0] r $10 devstat ide oscf devinit tf 0 0 0 devres $11 count count[7] count[6] count[5] count[4] count[3] count[2] count[1] count[0] $24 acc_x11l acc_x[7] acc_x[6] acc_x[5] acc_x[4] acc_x[3] acc_x[2] acc_x[1] acc_x[0] $25 acc_x11h 0 0 0 0 0 acc_x[10] acc_x[9] acc_x[8] $26 acc_y11l acc_y[7] acc_y[6] acc_y[5] acc_y[4] acc_y[3] acc_y[2] acc_y[1] acc_y[0] $27 acc_y11h 0 0 0 0 0 acc_y[10] acc_y[9] acc_y[8]
sensors 8 freescale semiconductor, inc. MMA690XKQ 2.1.1 device serial number a unique serial number is programmed into each device during manufacturing. the serial number is composed of the following information. lot numbers begin at 1 for all devices produced and are sequentia lly assigned. serial numbers begin at 1 for each lot, and are sequentially assigned. no lot will contain more devices than c an be uniquely identified by the 13-bit serial number. not all al low- able lot numbers and serial numbers will be assigned. 2.1.2 full-scale range full-scale range is indicated by the value programmed into devcfg0 and devcfg1. ranges for defined part numbers are shown in ta b l e 2 - 3 below. 2.1.3 device control register (devctl) a read-write register at address $0e suppor ts a number of device control operations as described in the following. reserved bits within devctl are always read as logic ?0? values. write operations involving devctl are effective approximately 1.0 s following negation of cs /reset . this delay must be considered if successive spi operations involving write to devctl followed by acceleration data read are conducted in the min- imum allowed transfer timing, as the acceleration result may in dicate lingering self-test or error status conditions. it is the refore recommended that acceleration data read operations be delayed by at least 1.2 s following writes to devctl. 2.1.3.1 reset control (res_1, res_0) a specific series of three writ e operations involving these two bits will cause the internal digital circuitry to be reset. the state of the remaining bits in the devctl register do not affect th e reset sequence, however any write operation involving this regis ter in which both res_1 and res_0 are cleared will terminate the sequence. to reset the internal digital circuitry, the following regi ster write operations must be performed in the order shown: 1. set res1. res0 must remain cleared. 2. set res1 and res0. 3. clear res1 and set res0. res1 and res0 are always read as logic ?0? values. table 2-2. serial number assignment bit function bit range content sn12 - sn0 serial number sn31 - sn13 lot number table 2-3. full-scale range part number register range bits full-scale range (g) rng[3] rng[2] rng[1] rng[0] m m a 6 9 0 0 k qd e v c f g 000003 . 5 d e v c f g 100003 . 5 m m a 6 9 0 1 k qd e v c f g 001015 . 0 d e v c f g 101015 . 0 table 2-4. device control register address register bit 7 6 5 4 3 2 1 0 $0e devctl res1 res0 ce pcm_en hpfb yinv st1 st0
sensors freescale semiconductor, inc. 9 MMA690XKQ 2.1.3.2 clear error (ce) setting this bit to a logic ?1? state will clear transient error st atus conditions. it is necessary to either set this bit or p erform a device reset if an error condition has been reported by the device before acceleration data transfer can be resumed. the device reset condition may be cleared only after device initialization has completed. error conditions and classification are described in section 3.1 . the state of this bit is always read as logic ?0?. 2.1.3.3 pcm enable (pcm_en) this bit controls the pcm_x and pcm_y outputs along with intern al circuitry which generates a pulse-code modulated signal from the acceleration result. when this bit is set, the pc m outputs are enabled. when cleared, pcm_x and pcm_y are driven to a logic low level. 2.1.3.4 high-pass filter bypass (hpfb) the high-pass filter is disabled through factory settings, t herefore writing this bit will have no effect. if read, this bit wi ll be ?0?. 2.1.3.5 y-axis signal inversion control (yinv) this control function is provided as a means to verify oper ation of the two-channel multiple xor which alternately provides x-axis and y-axis data to the dsp. an inverter block and multip lexor at the y-axis input to t he dsp are controlled by the yinv bit. setting this bit when st0 is set has the effect of changing the sign of acceleration in the y-ax is. operation of the yinv bit i s illustrated in figure 2-1 . y-axis inversion may be selected only during self-t est; the state of this bit has no effect when st0 is cleared. figure 2-1 y-axis inversion function self-test operations controlled by yinv al ong with st1 and st0 are summarized in the ta b l e 2 - 5 . 2.1.3.6 self-test control (st1, st0) bidirectional self-test control is provided through manipulation of these bits. st1 controls direction while st0 enables and di s- ables the self-test circuitry. st1 and st0 are always cleared fo llowing internal reset. when st0 is set, the high-pass filter i s by- passed and the values within the high-pass f ilter are frozen. both axes are affected simultaneously by the state of these bits. if the offset monitor is enabled, self-test activation in a single direction should be limited to less than 30 ms. communications protocol bits s2 - s1 are invert ed when self-test is activated, as described in section 3.2. offset correction is applied within the dsp, and is not affected by the state of the yinv bi t. consequently, inversion of the y-axis signal may result in saturation of the y-axis output value. correct operation of the dsp input multiplexor may be confirmed by performing the operations shown in figure 2-2 . table 2-5. self-test control operations yinv st1 st0 self-test operation x-axis y-axis x x 0 self-test disabled, y-axis signal inversion disabled 0 0 1 positive deflection 0 1 1 negative deflection 1 0 1 positive deflection negative deflection 1 1 1 negative deflection positive deflection dsp yinv ? converter sinc filter x-axis ? converter y-axis sinc filter st0 0 1
sensors 10 freescale semiconductor, inc. MMA690XKQ figure 2-2 dsp input multiplexor ve rification flow chart (y axis) 2.1.4 temperature sensor value (temp) this read-only register contains a signed value which provides a relative temperature indicati on. the temperature sensor is uncalibrated and its output for a given temper ature will vary from one device to the next. the value in this register increases with temperature. 2.1.5 device status register (devstat) this read-only register is accessible in all modes. 2.1.5.1 internal data error flag (ide) this flag will be set if a register data parity fault or a marginally programmed fuse is detected. device reset is required to clear this fault condition. if a parity error is associated with the da ta stored in the fuse array, this fault condition cannot be cl eared. this flag is disabled when the device is in test mode. 2.1.5.2 device initialization flag (devinit) this flag is set during the interval between negation of inte rnal reset and completion of device initialization. devinit is cle ared automatically. table 2-6. temperature sensor value register location bit function address register 7 6 5 4 3 2 1 0 $0f temp temp[7] temp[6] temp[5] temp[4] temp[3] temp[2] temp[1] temp[0] table 2-7. device status register location bit function address register 7 6 5 4 3 2 1 0 $10 devstat ide 0 devinit tf 0 0 0 devres yinv = 0, st1 = 0, st0 = 1 read acceleration (r 1 ) multiplexor r 1 > r 2 y n yinv = 0, st1 = 1, st0 = 1 read acceleration (r 2 ) yinv = 1, st1 = 0, st0 = 1 read acceleration (r 3 ) yinv = 1, st1 = 1, st0 = 1 read acceleration (r 4 ) r 3 r 4 y n verification successful multiplexor verification failed
sensors freescale semiconductor, inc. 11 MMA690XKQ 2.1.5.3 temperature fault flag (tf) this flag is set if the value reported by the on-chip temperature sensor exceeds specified limits. tf may be cleared by writing a logic ?1? value to the ce bit in devctl, provid ed that the fault conditi on is no longer detected. 2.1.5.4 device reset flag (devres) this flag is set during device initialization. a logic ?1? must be written to the ce bit in the device control register (devctl ) to clear this bit. except when communications protocol is active, this bit must be ex plicitly cleared following reset before accel era- tion results can be read from MMA690XKQ. 2.1.6 counter register (count) this read-only register provides the value of a free-running 8- bit counter derived fr om the primary oscillator. a five-bit pres caler divides the 4.0 mhz primary oscillator frequency by 32. thus, the value in the register increases by one count every 8.0 s, and the counter rolls over every 2.048 ms. 2.1.7 acceleration result registers these read-only registers contain accelerati on results produced by the dsp. the values in these registers are frozen by either of two events: ?cap /hold input at logic high level ?cs input at logic low level acceleration result registers are provided for each axis. acc_x11l/acc_x11h and acc_y11l/acc_y11h provide 11-bit re- sults. updates to acc_x11l/acc_x11h and acc_y11l/acc_y11h are halted upon reading the lower-byte register of either pair until the upper-byte register is read. there is no requirement to manipulate cap /hold when reading acc_x11l/acc_x11h or acc_y11l/acc_y11h, however acc_x11h or acc_y11h must be read after reading acc_x11l or acc_y11l, respective- ly, or further updates to the register pair will not occur. sign extension is applied to the upper five bits of acc_x11h and acc_y11h. if an error condition exists, the reserved value 0 will be read in place of 11-bit acceleration data. table 2-8 counter register location bit function address register 7 6 5 4 3 2 1 0 $11 count count[7] count[6] count[5] count[4] count[3] count[2] count[1] count[0] table 2-9. x-axis acceleration result registers location bit function address register 7 6 5 4 3 2 1 0 $24 acc_x11l acc_x[7] acc_x[6] acc_x[5] acc_x[4] acc_x[3] acc_x[2] acc_x[1] acc_x[0] $25 acc_x11h 0 0 0 0 0 acc_x[10] acc_x[9] acc_x[8] table 2-10. y-axis acceler ation result registers location bit function address register 7 6 5 4 3 2 1 0 $26 acc_y11l acc_y[7] acc_y[6] acc_y[5] acc_y[4] acc_y[3] acc_y[2] acc_y[1] acc_y[0] $27 acc_y11h 0 0 0 0 0 acc_y[10] acc_y[9] acc_y[8]
sensors 12 freescale semiconductor, inc. MMA690XKQ 2.2 voltage regulators separate internal voltage regulators supply fixed voltages to th e analog and digital circuitry. external filter capacitors are required, as shown in figure 1-5 . the voltage regulator module includes a voltage monitoring circ uitry which holds the device in reset following power-on until internal voltages have stabilized sufficiently for proper operat ion. the voltage monitor asserts internal reset when the extern al supply or internally regulated voltages fall below predetermined levels. a reference generator provides a st able voltage which is used by the ? converter. this circuit also requires an external filter capacitor. the voltage regulator module is illustrated in figure 2-3 and figure 2-4 . figure 2-3 power distribution c rega c ref c reg c ref c rega v cc voltage regulator voltage regulator reference generator v rega = 2.50 v digital logic dsp otp array primary oscillator otp array reference oscillator ? converter bandgap reference bias generator trim trim bias generator ? converter v bg v ref = 1.250v v reg = 2.50v bandgap reference v bga
sensors freescale semiconductor, inc. 13 MMA690XKQ figure 2-4 voltage monitoring 2.3 oscillator an internal oscillator operating at a nominal frequency of 4.0 m hz provides a stable clock source. the oscillator is factory trimmed for best performance. a clock generator blo ck divides the 4.0 mhz clock as needed by other blocks. 2.4 c reg monitor a monitor circuit is incorporated to ensure predictable operation of t he device in the event that th e connection to the externa l capacitor at the c reg pin (pin 8) fails, or the capacitor opens. the monitor disables the 2.5 v regulator which powers the digital circuitry for 2.0 s every 249.5 s. if the external capacitor is not present, voltage at the internal supply rail will drop below the internal reset threshold, continuously forc ing the device into reset. loss of communica tion from the device is a readily detect able condition. the x out and y out pins are driven to the low rail when the device is in the reset state. 2.5 clock monitor two independent oscillators are provided wit hin MMA690XKQ. one is factory-trimmed and provides the timing reference used throughout the device. the second oscillator acts as a referenc e for the first. if the frequency of these two oscillators varie s by more than 10%, an oscillator fault condition is determined. in normal operating mode, an osci llator fault will cause the d out pin to be forced to a continuous logic high state when cs is asserted, as described in section 3.1.1.2 . por v cc v rega v bg v reg v ref v bga refer to section 5.3 for power-on reset threshold limits. + - + - + - + - voltage divider voltage divider voltage divider voltage divider + - voltage divider + - voltage divider ov uv uv uv ov ov + - voltage divider uv
sensors 14 freescale semiconductor, inc. MMA690XKQ 2.6 internal reset controller four conditions can result in an internal reset. the initial power-on condition always results in a reset condition an internal voltage monitor will assert reset when the supply voltage or a r egulated output voltage falls below specified limits. this is r eferred to as a low voltage reset. externally, a hardware reset can be initiated by holding sclk high and driving the cs pin low for 512 s. finally, the device can be reset through a series of register write operations, as described in section 2.1.3.1 . 2.7 control logic a control logic block coordinates a number of activities within the device. these include: ? post-reset device initialization ? self-test ? operating mode selection ? data array programming ? device support data transfers 2.8 temperature sensor a temperature sensor provides input to the digital signal proce ssing block. device te mperature is incorporated into a correctio n value, which is applied to each acceleration result. the upper ei ght bits of the temperature sensor value are accessible throug h the temp register, described in section 2.1.4 . the temperature sensor output is cont inuously compared to under- or over-tem- perature limits of app roximately -40 and +110 c, respectively. a temperature fault conditio n is indicated if the temperature sensor value exceeds the under- or over-temperature limit. 2.8.1 temperature sensor monitor a monitor circuit associated with the temperature sensor is provided. the monitor will detect over- or under-temperature con- ditions as well as rapid fluctuations in te mperature sensor output such as would be related to failure of the sensor. if a temp erature related fault is detected, an error condition is indicated in lieu of acceleration data. rapid fluctuation of the temperature sensor output is detected by comparing the value of each sample to the previous value. this operation, as well as temperat ure limit detection is illustrated in figure 2-5 . a fault condition is indicated if predetermined limits are exceeded.
sensors freescale semiconductor, inc. 15 MMA690XKQ figure 2-5 temperature sensor monitor flow chart | t | > 3? read 10-bit temperature sensor value (t p ) n t = t p - t r t r = t p start end t p > otl? n y y t p < utl? n y set temperature fault flag tsmen == 1? y n otl: over-temperature limit utl: under-temperature limit ssl: sample-to-sample limit
sensors 16 freescale semiconductor, inc. MMA690XKQ 2.9 spi the spi is a full bidirectional port which is us ed for all configuration and control functions. 2.10 self-test interface the self-test interface provides a mechanism for applying a calibr ated voltage to the g-cell. this results in deflection of the proof mass, causing reported acceleration results to be offset by a specified amount. control of the self-test interface via th e spi is accommodated through write operations involving the devctl register at address $0e, described in section 2.1.3 . 2.11 ? converters two sigma delta converters provide the in terface between the g-cell and digital signal processing block. the output of each ? converter is a data stream at a nominal frequency of 1.0 mhz. 2.12 digital signal processing block a digital signal processing (dsp) block is used to perform all filtering and correction operations. a diagram illustrating the signal processing flow within the dsp block is shown in figure 1-1 . the dsp operates at 2.0 mhz , twice the frequency of the ? converters. the two interleaved bit streams from the ? converters are processed simultaneously within the dsp. each MMA690XKQ device is factory programmed to select the acce leration range. filter characteristics for the x- and y-axes are customer programmed. 2.12.1 low-pass filter low-pass filtering occurs in two stages. the serial data stream produced by the ? converters is decimated and converted to parallel values by a sinc filter. parallel data is then pr ocessed by an infinite impulse response (iir) low-pass filter. a selection of low-pass filter characterist ics are available. the cutoff frequency (f c ) and rate at which acceleration samples are determined by the device (t s ) vary depending upon which filter is chosen. powe r consumption is also affected, as higher sample rates require greater dsp activity, which in turn requires more supply current. response parameters for available low-pass filter are summarized in a.2 .
sensors freescale semiconductor, inc. 17 MMA690XKQ section 3 serial communications digital data communication is completed through synchronous seri al transfers via the spi port. conventional spi protocol is employed, acting as a slave device observing cpol = 0, cpha = 0, msb first. all spi transfers are 16-bits in length, and employ parity detection to ensure data integrity. during each spi transfer, an odd number of bits received at d in must be set to a logic ?1? state, or a transient exception condition will be reported during the subsequent transfer. in all normal spi responses, an odd num- ber of bits transmitted on d out will be set to a logic ?1? state. besides parity detection and generation, several other data integrity features are incorporated into the transfer protocol. 3.1 exception conditions under certain conditions, the MMA690XKQ will respond to serial commands with a word, which indicates that an exception condition has been detected. response varies according to the co mmunication protocol selected. exceptions fall into five class- es and are prioritized. if multiple exception conditions are detected, only the exce ption of highest priority is reported. a reset exception condition exists following any device reset. i mmediately following reset, a device initialization condition w ill be indicated until internal initialization of the circuitry has completed. following internal initialization, a device reset ex ception condition exists until explicitly cleared by writing a logic ?1? to the ce bit in devctl. transient exception conditions result from data transmission erro rs such as data parity faults, an invalid number of clock cycles, etc. these exceptions ar e indicated during th e following spi transfer o peration. these excepti ons do not require an ex- plicit operation to be cleared. behavioral exception conditions are defined as those which affect acceleration data results but do not indicate an error condi- tion. in MMA690XKQ, the two behavioral exceptions are activation of self-test and a hold conditi on resulting from the external cap /hold pin being driven to a logic high state. register operatio ns are unaffected by behavioral exceptions. acceleration data transfers will complete, with the s/t1 and s/t0 bits indica ting that one or both behaviora l exception conditions exist. see section 3.2 for behavioral exceptions report ed by the communications protocol. critical error exceptions exist when an internal fault, which affects the reliability of device operation or acceleration resul ts, is detected. if a critical error condition exists, an invalid data va lue is produced by the device in lieu of acceleration results . register operations are unaffected except for the stat e of s[2:0]. some critical errors, such as temperature fault, may be cleared by writing a logic ?1? to the ce bit in devctl, provided the u nderlying fault condition no longer persists. other critical error conditions require reset of th e device to clear. 3.1.1 defined exceptions 3.1.1.1 internal data error class: critical error during reset, a number of internal registers are loaded from a fuse array which stores factory-programmed values. the resis- tance of each fuse is measured and compared to thresholds to ensure integrity of programmed data. additionally, the register array is continuously monitored for correct parity at all time while the device is powered. if either the margin test or parity verifi- cation fail, an internal data error exception is reported. device reset is required to clear this exception condition. 3.1.1.2 internal oscillator fault class: critical error if an oscillator fault c ondition is detected, d out is driven high continuously when cs is asserted, as illustrated in figure 3-1 . device reset is required to clear this exception condition. figure 3-1 oscillator failure response sclk d out cs
sensors 18 freescale semiconductor, inc. MMA690XKQ 3.1.1.3 device initialization class: reset following a reset condition, the device requires a period of time to complete initialization of the dsp and internal registers. if multiple spi transfers are attempted during this initialization period, the second and all subsequent transfers will result in this status. the first transfer following reset, regardless of the state of initialization returns device reset status. this exception condition is cleared automatic ally upon completion of device initialization. 3.1.1.4 temperature fault class: critical the internal temperature sensor value exceeds the allowable limits for the device. this exception condition may be cleared by writing a logic ?1? to the ce bit in d evctl, provided that the temperature has retu rned to within the operating limits of th e device. 3.1.1.5 unexpected axis selection class: transient an acceleration data request has been received wi th an axis specificatio n which is not supported. this exception condition is repor ted during the subsequent transfer. 3.1.1.6 device reset class: reset this exception condition is latched any time the device undergoes reset. device response will indicate the exception condition in lieu of acceleration data.the device re set exception condition must be explicitly cleared by writing a logic ?1? to the ce bit in devctl. 3.1.1.7 spi clock fault class: transient a spi clock fault may result from the following conditions: ? the number of rising clock edges detected while cs is asserted is not equal to the expected number for the selected communications protocol ? sclk is high when cs is asserted this exception condition is repor ted during the subsequent transfer. 3.1.1.8 d in parity fault class: transient a parity error was detected on d in during a data transmission. this exception condition is repor ted during the subsequent transfer. 3.1.1.9 hold condition a hold condition exists when the cap /hold pin is driven to a logic high level. self-test activation is controlled through con- figuration of st1 and st0 in devctl. 3.1.1.10 self-t est activation class: behavioral the device provides two status bits in its response which will indicate a behavioral exception condition if a hold condition exists or self-test is activated. as these are not error conditions, device res ponse is otherwise unaffected. refer to section 3.2.1 for details regarding device response to behavioral exception conditions. a hold condition exists when the cap /hold pin is driven to a logic level high leve l. self-test activation is controlled through configuration of st1 and st0 in devctl.
sensors freescale semiconductor, inc. 19 MMA690XKQ 3.1.2 exception priority ta b l e 3 - 1 provides a summary of exception conditions and order of priority. if an offset fault condition is detected simu ltaneously in both the x- and y-axes, only the x-axis exception is reported by the device. hold condition and self-test exceptions have equal prio rity; if both exceptions exist simultaneously, both are reported by the device. 3.2 communications protocol the communications protocol provides 11-b it acceleration data along with enhanced status notification in the event that an exception condition is det ected. all transfers are 16-bits in length, with the intended operation indicated by a two-bit transf er type code transmitted by the spi master. device response depends upon the transfer type code and the in ternal state of the device. if no exception condition has been detected, the device returns register or acceleration data as requested. if an exception cond ition exists, response depends upo n the requested operation and the e xception. exceptions are divided into four classes: behavioral, reset, transient, and critical . cer- tain operations, such as register data write and register pointer write, will not be completed if an exception condition is det ected during the associated spi transfer. all exception conditions detected by MMA690XKQ are listed in table 3-1 . response to ex- ceptions is described below, and summarized in table 3-3 . if both t1 and t0 are set to a logic ?1? state, an inva lid axis selection exception will be reported by the device. 3.2.1 device response device response depends upon exception conditions which may be pr esent at the time the transfer takes place. in case of multiple exceptions, the exception class of highest priority will determine response. table 3-1. exception conditions condition status bit class spi clock fault, previous transfer ? transient d in parity fault, previous transfer ? transient internal data error ide critical error internal oscillator fault ? critical error device initialization devinit reset device reset devres reset temperature fault tf critical error invalid axis selection ? transient hold condition ? behavioral self-test ? behavioral table 3-2. transfer type codes t1 t0 transfer type 0 0 register operation 0 1 x-axis acceleration data 1 0 y-axis acceleration data 1 1 unused
sensors 20 freescale semiconductor, inc. MMA690XKQ st = self-test active commands and response under normal and exception condition s are summarized in the following tables. note that only devctl at address $0e is writable when the device is in its normal operating mode. p: parity t[1:0] transfer type code note that only devctl is writable when the device operates in normal operating mode. attempts to write other registers do not constitute a fault condition, but have no effect. p: parity t[1:0] transfer type code table 3-3. device response, exception conditions exception command response priority class st hold t1 t0 s2 s1 s0 register acceleration data transient x x x x 1 1 1 status code status code highest reset x x t1 t0 1 1 1 as requested $7ff 2 critical x x 1 1 1 2 behavioral 1 1 0 t1 t0 as requested 2 1 0 1 t1 t0 2 0 1 1 t1 t0 2 none 0 0 0 t1 t0 lowest table 3-4. normal response summary operation bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 acceleration data read command t1 t0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 response 0 t1 t0 p d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 register pointer read command 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 response 0 0 0 0 0 p 0 0 a7 a6 a5 a4 a3 a2 a1 a0 register pointer write command 0 0 0 1 0 p 0 0 a7 a6 a5 a4 a3 a2 a1 a0 response 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 register data read command 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 response 0 0 0 1 0 p 0 0 d7 d6 d5 d4 d3 d2 d1 d0 register data write command 0 0 1 1 0 p 0 0 d7 d6 d5 d4 d3 d2 d1 d0 response 0 0 0 1 1 p 0 0 a7 a6 a5 a4 a3 a2 a1 a0 table 3-5. behavioral response summary, one exception condition operation bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 acceleration data read command t1 t0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 response 1 t1 t0 p d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 register pointer read command 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 response 1 1 1 0 0 p 0 1 a7 a6 a5 a4 a3 a2 a1 a0 register pointer write command 0 0 0 1 0 p 0 0 a7 a6 a5 a4 a3 a2 a1 a0 response 1 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 register data read command 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 response 1 1 1 1 0 p 0 1 d7 d6 d5 d4 d3 d2 d1 d0 register data write command 0 0 1 1 0 p 0 0 d7 d6 d5 d4 d3 d2 d1 d0 response 1 1 1 1 1 p 0 1 a7 a6 a5 a4 a3 a2 a1 a0
sensors freescale semiconductor, inc. 21 MMA690XKQ behavioral exception conditions exist if self-test is active or the cap /hold input is in a logic high state. MMA690XKQ will re- spond as shown in table 3-5 if either exception condition exists. if both exce ption conditions are true, response is as shown in ta b l e 3 - 4 . p: parity t[1:0] transfer type code a special case exists if an internal oscillator fault is detected. this critical e rror condition results in d out being driven high continuously while cs is asserted, as detailed in section 3.1.1.2 . p: parity t[1:0] transfer type code table 3-6. critical/reset exception response detail operation bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 acceleration data read command t1 t0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 response 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 register pointer read command 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 response 1 1 1 0 0 p 1 0 register address register pointer write command 0 0 0 1 0 p 0 0 register address response 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 register data read command 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 response 1 1 1 1 0 p 1 0 register data register data write command 0 0 1 1 0 p 0 0 register data response 1 1 1 1 1 p 1 0 register address table 3-7. transient exception response detail operation bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 acceleration data read command t1 t0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 response 1 1 1 p reserved value (refer to table 3-8 ) 0 register pointer read command 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 response 1 1 1 0 0 p 1 1 status code register pointer write command 0 0 0 1 0 p 0 0 register address response 1 1 1 0 1 p 1 1 status code register data read command 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 response 1 1 1 1 0 p 1 1 status code register data write command 0 0 1 1 0 p 0 0 register data response 1 1 1 1 1 p 1 1 status code
sensors 22 freescale semiconductor, inc. MMA690XKQ 3.2.2 acceleration data transfer the format of an acceleration data transfer is illustrated in figure 3-2 . response to acce leration data transfers is summarized in ta b l e 3 - 8 . note that a number of reserved values are defined to indicate error exceptions. MMA690XKQ will produce signed or unsigned data depending upon the state of the sd bit in the dspcfg register, as described in section 2.1.4 . t[1:0] transfer type code s[2:0]: status code figure 3-2 communications protocol, acceleration data transfer table 3-8. range of output, communications protocol 11-bit data value definition unsigned decimal hex 2047 7ff critical/reset exception value 2046 7fe invalid axis selection 2045 7fd internal signal path overflow 2044 7fc overrange value 2043 7fb maximum positive signal level ? ? ? ? ? ? 1024 400 zero signal level ? ? ? ? ? ? 5 005 minimum negative signal level 4 004 underrange value 3 003 internal signal path underflow 2 002 spi clock fault 1 001 d in parity fault 0 000 reserved value sclk bit 15 mosi miso cs 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 d5 d4 d3 d2 d1 d0 0 t1 t0 s2 s1 d6 d7 d8 d9 d10 s0 p 00000000000000
sensors freescale semiconductor, inc. 23 MMA690XKQ 3.2.3 register operations register operations involve four transfer types: register pointer write or read, and register data write or read. the basic for mat for register operations is illustrated in figure 3-3 . response from MMA690XKQ under normal conditions is illustrated. specific details for each transfer type are provided in the command/response summaries provided in section 3.2.1 . t[1:0] transfer type code s[2:0]: status code a /d: address /data r /w: read /write ec[1:0]: exception class (refer to table 3-9 below) d/a[7:0]: data or address, depending upon transfer type and status figure 3-3 communications protocol, register operations sclk bit mosi miso cs r /w p 0 0 d/a7 d/a6 d/a5 d/a4 d/a3 d/a2 d/a1 d/a0 0 t1 t0 a /d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 d/a6 d/a5 d/a4 d/a3 d/a2 d/a1 d/a0 s2 s1 d/a7 ec0 ec1 p r /w s0 a /d table 3-9. exception class encoding ec1 ec0 exception class 0 0 no exception 0 1 behavioral (one exception) 1 0 critical/reset 1 1 transient
sensors 24 freescale semiconductor, inc. MMA690XKQ 3.3 representation 3.3.1 overrange response positive acceleration levels wh ich exceed the full-scale range of the device fall into two categories: overrange and overflow. overrange conditions exist when the signal level is beyond the full-scale range of the device but within the computational limi ts of the dsp. an overflow condition occurs if the output of t he low-pass filter equals or exceed s the maximum digital value which can be output from the sinc filter. sinc f ilter saturation will occur before the internal data path width is exceeded. at 25 c and ovld = 0, the sinc filter will not saturate at sustained acceleration levels with the range of 200g. the dsp operates predictably under all cases of overrange, although the signal may include residual high frequency components for some time after returning to the normal range of operation due to non-linear effects of the sensor. if an overflow condition occurs, the signal is intern ally clipped. the dsp will recover from an overflow condition within a few sample times after the input signal returns to the input range of the dsp. due to internal clipping within the dsp, some hi gh-frequency artifacts may be present in the output following an ov er- flow condition. for negative acceleration levels, corresponding und errange and underflow conditions are defined. 3.4 cap /hold input the cap /hold input provides a system-level synch ronization mechanism. when driven high, transfer of acce leration results from the dsp to the spi buffers does not occur. the dsp co ntinues its normal operation re gardless of the state of cap /hold. data read from the device when cap /hold is high will reflect the last values availa ble from the dsp at the time of the signal transition. table 3-10. nominal 11-bit acceleration data values 11-bit unsigned digital value nominal acceleration 3.5g range 5.0g range 2047 critical/reset exception value 2046 invalid axis selection 2045 overflow 2044 overrange 2043 +3.50g +5.00g 2042 +3.50g +5.00g 2041 +3.49g +4.99g ? ? ? ? ? ? ? ? ? 1027 +10.3 mg +14.7 mg 1026 +6.87 mg +9.81 mg 1025 +3.43 mg +4.91 mg 1024 0g 0g 1023 -3.43 mg -4.91 mg 1022 -6.87 mg -9.81 mg 1021 -10.3 mg -14.7 mg ? ? ? ? ? ? ? ? ? 7 -3.49g -4.99g 6 -3.50g -5.00g 5 -3.50g -5.00g 4 underrange 3 underflow 2 spi clock fault 1 d in parity fault 0 reserved
sensors freescale semiconductor, inc. 25 MMA690XKQ section 4 operating modes MMA690XKQ operates in one of two modes, factory test progr amming mode and normal operating mode. factory test and programming mode is entered only when cert ain conditions are met, and provides suppo rt for programming of customer-defined data. normal mode is entered by def ault when the device is powered on. 4.1 normal operating mode normal mode is entered whenever the device is powered and the v pp pin is held at or below the level of v cc . in normal mode, acceleration data and device support data transfers are supported. 4.1.1 power-on reset upon application of voltage at the v cc pin, the internal regulators will begin driving the internal power supply rails. the c reg and c rega pins are tied to the internal rails. as voltages at v cc , c reg and c rega rise, the device becomes operational. an in- ternal reset signal is asserted at this time. separate comparators on monitor all three voltages, and when all are above specif ied thresholds, the reset signal is negated and the device begins its initialization process. 4.1.2 device initialization following any reset, the device completes a sequence of operations which initialize internal circuitry. device initialization i s completed in two phases. during the first phase, the fuse array is read and its contents are transferred to mirror registers. p ower to the fuse array is then removed to reduce supply current l oad. a voltage reference used withi n the sensor interface stabilize s during the second phase. if the hpfsel bit is set in the dsp co nfiguration register (dspcfg), the high-pass filter is also init ial- ized during phase two. the device will not respond to spi accesses during initialization phase one. acceleration results are not available during ini- tialization phase two, however the spi is functional and regi ster operations may be performed. if an acceleration data access i s attempted, the device will respond with non-acceleration data . the specific response depends upon the communications proto- col selected. the first initialization phase requires approximately 800 s to complete. the second phase completes in appr oximately 3.0 ms if no high-pass filter is selected, and 200 ms if the hpfsel bit is programmed to a logic ?1? st ate. the devinit bit in the devi ce status register (devstat) remains set following reset until the second phase of dev ice initialization completes. following completion of th e device initialization, the devres bit in devstat may be cleared by writing a logic ?1 ? value to ce in devctl. this operation will clear the device reset exception. once cleared, register operations may be completed or accel- eration data values may be read from the device in any desired sequence.
sensors 26 freescale semiconductor, inc. MMA690XKQ section 5 performa nce specification 5.1 maximum ratings maximum ratings are the extreme limits to which the device can be exposed without permane ntly damaging it. the device contains circuitry to protect the inputs against damage from high static voltages; ho wever, do not apply voltages higher than t hose shown in the table below. keep input and output voltages within the range v ss v v cc . 5.2 operating range the operating ratings are the limits normally expected in the application and define the range of operation. rating symbol value unit supply voltage v cc -0.3 to +7 v (1) 1.verified by characterization, not tested in production. c reg , c rega , c ref v reg -0.3 to +3 v (1) v pp v reg -0.3 to +11 v (1) sclk, cs , d in , cap /hold, pcm_x, pcm_y v in -0.3 to v cc + 0.3 v (1) d out (high impedance state) v in -0.3 to v cc + 0.3 v (1) current drain per pin excluding v cc and v ss i1 0m a (1) powered shock (six sides, 0.5 ms duration) g pms 1500 g (1) unpowered shock (six sides, 0.5 ms duration) g shock 2000 g (1) drop shock (to concrete surface) h drop 1.2 m (1) electrostatic discharge human body model (hbm) charge device model (cdm) machine model (mm) v esd v esd v esd 2000 500 200 v v v (1) (1) (1) storage temperature range t stg -40 to +125 c (1) characteristic symbol min typ max units supply voltage standard operating voltage, 3.3v operating range standard operating voltage, 5.0v operating range v cc v cc v l +3.15 +4.75 +3.3 +5.0 v h +3.45 +5.25 v v (1) (1) 1.characterized at all values of v l and v h . production test is conducted at typical voltage unless otherwise noted. operating temperature range t a t l -40 ? t h +105 c (2) 2.parameters tested 100% at final test.
sensors freescale semiconductor, inc. 27 MMA690XKQ 5.3 electrical characteristics v l (v cc - v ss ) v h , t l t a t h , | t a | < 4.0 k/min. unless otherwise specified * indicates a freescale critical characteristic. characteristic symbol min typ max units supply current drain v cc = 5.25 v, t s = 64 s *i dd ??8 . 0m a (1) 1.parameters tested 100% at final test. power-on reset threshold (see figure 5-1 ) v cc c reg c rega c ref power-on reset threshold (see figure 5-1 ) v cc c reg c rega c ref hysteresis (vpor_n - vpor_a, see figure 5-1 ) v cc c reg c rega c ref v por_n v por_n v por_n v por_n v por_a v por_a v por_a v por_a v hyst v hyst v hyst v hyst 2.77 1.80 2.18 1.11 2.77 1.80 2.18 1.11 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? 3.15 2.32 2.50 1.29 2.95 2.10 2.31 1.19 388 300 261 150 v v v v v v v v mv mv mv mv (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) 2.verified by characteriza tion, not tested in production. internally regulated voltages c reg c rega (3) c ref 3.tested at v cc = v l and v cc = v h . * * * v dd v 2.5 v ref 2.42 2.42 1.20 2.50 2.50 1.25 2.58 2.58 1.29 v v v (1) (1) (1) (1) external filter capacitor (c reg , c rega ) value esr (including interconnect resistance) c reg esr 800 ? 1000 ? 200 nf m (2) (2) power supply coupling ? ? 0.004 digit/mv (2) nonlinearity nl out -1.0 ? 1.0 % fsr (2) noise (1.0 hz-1.0 khz) n sd ? ? 140 g/ hz (2) sensitivity 3.5g range 11-bit data 5.0g range 11-bit data * * sens sens ? ? 3.43 4.91 ? ? mg/digit mg/digit (1) (1) sensitivity error 3.5g range 5.0g range * sens -3.0 -3.5 ? +3.0 +3.5 % % (1) (1) offset at 0 g 11-bit unsigned data absolute offset error -40c t a 105 c variation from measured absolute offset error -40c t a 105 c * * * d out d out ? d out ? -20.4 -14.6 1024 ? ? ? +20.4 +14.6 digit digit digit (1) (1) (1)
sensors 28 freescale semiconductor, inc. MMA690XKQ electrical characteristics (continued) v l (v cc - v ss ) v h , t l t a t h , | t a | < 4 k/min unless ot herwise specified. * indicates a freescale critical characteristic. characteristic symbol min typ max units range of output 11-bit data, unsigned normal critical fault value invalid axis selection positive acceleration overflow code positive acceleration overrange code negative acceleration underrange code negative acceleration underlfow code spi clock fault din parity fault unused code range cfu iau of u or u ur u uf u scfu pfu unused 5 ? ? ? ? ? ? ? ? ? ? 2047 2046 2045 2044 4 3 2 1 0 2043 ? ? ? ? ? ? ? ? ? digit digit digit digit digit digit digit digit digit digit (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 1.functionality verified 100% via scan. timi ng characteristic is directly determ ined by internal os cillator frequency. output value on overrange 11-bit data: 2043 3.5g range 5.0g range 11-bit data: 5 3.5g range 5.0g range g over g over g under g under +3.22 +4.63 -3.79 -5.38 +3.50 +5.00 -3.50 -5.00 +3.79 +5.38 -3.22 -4.63 g g g g (2) (2) (2) (2) 2.verified by characterization, not tested in production. maximum acceleration without sa turation of internal circuitry (ovld = 0) g sat < -12 ? > +12 g (2) self-test output change (3) t a = 25 c -40 t a 105 c 3.self-test deflection is trimmed in posit ive direction. deflection in negative dire ction is approximately equal in magnitude. * * st st 472 437 525 525 578 630 mg mg (4) (4) 4.parameters tested 100% at final test. cross-axis sensitivity (5) v zx v yx v zy 5.verified by characterization. conformance guaranteed to 20 ppm. v zx v yx v zy -3 -3 -3 ? ? ? +3 +3 +3 % % % (2) (2) (2) output high voltage d out (i load = -100 a) v oh 0.85 ? ? v cc (6) 6.parameters tested 100% at unit probe. output low voltage d out, (i load = 100 a) v ol ??0 . 1v cc (6) output loading (d out ) load resistance load capacitance z out c out 47 ? ? ? ? 35 k pf (2) (2) input high voltage cs /reset , sclk, d in , cap /hold v ih 0.65 ? ? v cc (6) high impedance leakage current d out , input voltage = v cc or v ss i il -3 ? +3 a (4) input low voltage cs /reset , sclk, d in , cap /hold v il ??0 . 2v cc (6) input current high (at v ih ) sclk, d in , cap /hold v pp (internal pull-down resistor) low (at v il ) cs /reset i ih r in i il -30 190 30 -50 270 50 -260 350 260 a k a (6) (6) (6)
sensors freescale semiconductor, inc. 29 MMA690XKQ 5.4 control timing v l (v cc - v ss ) v h , t l t a t h , | t a | < 4 k/min unless ot herwise specified figure 5-1 power-up timing figure 5-2 cs reset timing characteristic symbol min typ max units dsp low-pass filter cut-off frequency filter order f c(lpf) o lpf 47.5 50.0 2 52.5 hz 1 (1) (1) 1.functionality verified 100% via scan. ti ming characteristic is directly deter mined by internal oscillator frequency. power-on recovery time por negated to cs low power applied to x out , y out valid t op t xy ? ? ? ? 840 15 s ms (1) (2) 2.parameters tested 100% at final test. internal oscillator frequency f osc 3.8 4.0 4.2 mhz (2) clock monitor threshold f mon 3.6 ? 4.4 mhz (1) chip select to internal reset (see figure 5-2 ) t csres 486 512 538 s (1) serial interface timing (see figure 5-3 ) clock period cs asserted to sclk high data setup time data hold time sclk high to data out sclk high to cs negated cs negated to cs asserted t sclk t csclk t dc t cdin t cdout t chcsh t csn 120 60 20 10 ? 60 600 ? ? ? ? ? ? ? ? ? ? ? 50 ? ? ns ns ns ns ns ns ns (3) (3) (3) (3) (3) (3) (3) 3.verified by characterization, not tested in production. sensing element natural frequency sense element bandwidth (-3.0 db) f n bw gcell ? ? 3 1.2 ? ? khz khz (3) (3) v cc 5.5v v por_n v por_a por internal reset cs t csres sclk
sensors 30 freescale semiconductor, inc. MMA690XKQ figure 5-3 serial interface timing t clk t dc t cdin sclk d in d out t cdout data valid cs t csclk t csn t chcsh
sensors freescale semiconductor, inc. 31 MMA690XKQ 5.5 package information the following documents provide a case outline drawing and information regarding printed wiring board mounting for the MMA690XKQ device. for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. the board mounting application note an3111 can be also located on the freescale web site. 5.5.1 package dimensions page 1 of 3 98asa10571d issue b case 1477-02 16 lead qfn
sensors 32 freescale semiconductor, inc. MMA690XKQ page 2 of 3 98asa10571d issue b case 1477-02 16 lead qfn
sensors 33 freescale semiconductor, inc. MMA690XKQ page 3 of 3 98asa10571d issue b case 1477-02 16 lead qfn
sensors 34 freescale semiconductor, inc. MMA690XKQ appendix a digital filter characteristics response curves for filter options are provided in this appendix. a.1 sinc filter characteristics figure a-1 sinc filter response, t s = 32 s 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 x 10 5 ?8000 ?6000 ?4000 ?2000 0 frequency (hz) phase (degrees) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 x 10 5 ?200 ?150 ?100 ?50 0 frequency (hz) magnitude (db) sinc filter: r =32, n =3, fs =1000000
sensors freescale semiconductor, inc. 35 MMA690XKQ a.2 low-pass filter characteristics figure a-2 low-pass filter, f c = 50 hz, poles = 2, t s = 32 s 10 1 10 2 ?30 ?25 ?20 ?15 ?10 ?5 0 frequency (hz) gain (db) frequency response 10 1 10 2 0 100 200 frequency (hz) group delay (samples) group delay 10 1 10 2 ?5 0 5 frequency (hz) phase (radians) phase response
sensors 36 freescale semiconductor, inc. MMA690XKQ table 6. revision history revision number revision date description of changes 4 03/2012 ? added safeassure logo, changed first paragr aph and disclaimer to include trademark information. 5 08/2012 ? changed device numbers to include ?k? suffix. ? changed aec-q100 qualified, rev. g to rev. f. ? section 1.4.12, added ? table 2-1: corrected addr $0a and $0b bits 7 and 6 from 0 and 1 to 1 and 0. ? section 5.3 electrical characteristics table under offset at 0 g: changed offset error to absolute offset error, removed temperature range t a = 25c, removed 11-bit data line, added temperature range -40c t a 105c and values. added variation from measured absolut e offset error with temperature range of -40c t a 105c and values.
document number: MMA690XKQ rev. 5 08/2012 information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the app lication or use of an y product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in differen t applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s technica l experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions. how to reach us: home page: freescale.com web support: freescale.com/support freescale, the freescale logo, altivec, c-5, codetest, codewarrior, coldfire, c-ware, energy efficient solutions logo, kinetis, mobilegt, powerquicc, processor expert, qoriq, qorivva, starcore, symphony, and vortiqa are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. airfast, beekit, beestack, coldfire+, corenet, flexis, magniv, mxc, platform in a package, qoriq qonverge, quicc engine, ready play, safeassure, smartmos , turbolink, vybrid, and xtrinsic are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2012 freescale semiconductor, inc.

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